`timescale 1 ns / 1 ns

module tb_pll_led();

reg sys_clk;
reg sys_rst_n;
wire [3:0] led;

//产生复位
initial begin
    sys_rst_n = 1'b0;
    #200
    sys_rst_n = 1'b1;
end

//产生时钟
initial sys_clk = 1'b0;
always #10 sys_clk = ~sys_clk;

//例化仿真模块
pll_led #(
	.LED_PERIOD(500)
)
tb_pll_led_inst0(
    .sys_clk(sys_clk),
    .sys_rst_n(sys_rst_n),
    
    .led(led)
);

endmodule